False bus glitches are eliminated, but of course some bus signal propagation delays are still introduced and these delays can act to limit the maximum bus clock speed.įigure 2: Simple 5kHz opto-electrical isolation circuitįigure 2 shows the simple circuit that uses the opto-isolation of I 2 C-bus signals using low-cost 4N36 opto-couplers. It never blocks any signals, it uses instead different logic voltage levels that are all placed below the normal bus logic “low” level and are therefore transparent to the connected I 2 C chips. It introduces special logic voltage levels on one of its inputs to prevent bus latching. The way to eliminate these glitches is by using an I 2 C opto-isolation buffer IC. This is a false bus signal that can lead to problems. After another switch-on delay the photo-transistor in IC2 turns on and SDA is pulled down again to the correct state, ending the unwanted “glitch.” But notice SDA was high during the time taken for IC2 to turn off plus the time taken for IC1 to turn on. After IC1 turns off, R3 can source current to pin 2 of the LED in opto-coupler IC2 and current flows, via the LED, to -SDA that's being held low. With SDA high, the LED of opto-coupler IC1 turns off and after some delay time its photo-transistor turns off. This represents the start of an unwanted “glitch” of the I 2 C-bus at SDA. SDA immediately goes high because there's nothing to hold it low the photo-transistor in IC2 isn't on. The photo-transistor in IC1 remains on, so there is no current in the LED of IC2. It's already low so the -SDA bus doesn't change state. The photo-transistor in IC1 turns on and the isolated -SDA is pulled low via diode D2. Current in R2 turns on the LED in opto-coupler IC1. Let's try this test on the circuit of Figure 1. If the system conforms to the I 2 C protocol the first side should just stay low, held low by the second side. Then release the drive on the first side. Drive one side of the isolating circuit low, then, holding that first side low, drive the other side low. You can apply a simple test to check whether an isolating circuit will generate unwanted glitches on the bus. The challenge to optically isolate the I 2 C-bus has always been to effectively split the bidirectional I 2 C signals into unidirectional data streams and recombine them again. Unfortunately it's not so simple to provide opto-isolation of the I 2 C-bus because the I 2 C clock and data signals are both bidirectional signals while opto-couplers can only handle unidirectional signals. These and similar applications need galvanic isolation, so including opto-couplers in I 2 C-bus signal wires is obviously attractive. Additionally, medical patient-monitoring equipment needs to operate without any common physical interconnection wiring to form a safety isolation barrier to prevent any chance of electrocution. Some of these systems are connected to telephone lines or to electronic switches that are directly connected to the high-voltage AC main power supply and should be electrically isolated. The inter-integrated circuit bus (I 2 C-bus) provides an attractive maintenance and control communication interface between parts of a system since it uses only two signal wires yet has powerful addressing and a reasonably fast, up to 400kHz bidirectional data handling capability. This hands-on article shows how to isolate I 2 C devices without giving up the advantages of this popular bus. In some systems, though, these chips need to be opto-isolated to avoid damage from stray electrical current in harsh environments. The I 2 C-bus is fabulously popular and successful as a low-cost way to attach chips together in small embedded systems.
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